• 主题
高级搜索  >
历史搜索 清空历史
首页> 外文OA文献 >The impact of self-heating and SiGe strain-relaxed buffer thickness on the analog performance of strained Si nMOSFETs
【2h】

The impact of self-heating and SiGe strain-relaxed buffer thickness on the analog performance of strained Si nMOSFETs

机译：自热和SiGe应变缓和缓冲层厚度对应变Si nMOSFET的模拟性能的影响

代理获取
本网站仅为用户提供外文OA文献查询和代理获取服务，本网站没有原文。下单后我们将采用程序或人工为您竭诚获取高质量的原文，但由于OA文献来源多样且变更频繁，仍可能出现获取不到、文献不完整或与标题不符等情况，如果获取不到我们将提供退款服务。请知悉。
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

The impact of the thickness of the silicon–germanium strain-relaxed buffer (SiGe SRB) on the analog performance of strained Si nMOSFETs is investigated. The negative drain conductance caused by self-heating at high power levels leads to negative self-gain which can cause anomalous circuit behavior like non-linear phase shifts. Using AC and DC measurements, it is shown that reducing the SRB thickness improves the analog design space and performance by minimizing self-heating. The range of terminal voltages that leverage positive self-gain in 0.1 μm strained Si MOSFETs fabricated on 425 nm SiGe SRBs is increased by over 100% compared with strained Si devices fabricated on conventional SiGe SRBs 4 μm thick. Strained Si nMOSFETs fabricated on thin SiGe SRBs also show 45% improvement in the self-gain compared with the Si control as well as 25% enhancement in the on-state performance compared with the strained Si nMOSFETs on the 4 μm SiGe SRB. The extracted thermal resistance is 50% lower in the strained Si device on the thin SiGe SRB corresponding to a 30% reduction in the temperature rise compared with the device fabricated on the 4 μm SiGe SRB. Comparisons between the maximum drain voltages for positive self-gain in the strained Si devices and the ITRS projections of supply-voltage scaling show that reducing the thickness of the SiGe SRB would be necessary for future technology nodes.
机译：研究了硅锗应变缓和缓冲器（SiGe SRB）的厚度对应变Si nMOSFET的模拟性能的影响。在高功率水平下由自发热引起的负漏极电导会导致负自增益，这可能导致异常电路行为，例如非线性相移。使用交流和直流测量结果表明，减小SRB厚度可通过最小化自发热来改善模拟设计空间和性能。与在4 nm厚的传统SiGe SRB上制造的应变Si器件相比，在425 nm SiGe SRB上制造的0.1μm应变Si MOSFET中利用正自增益的端子电压范围增加了100％以上。与Si控制相比，在薄SiGe SRB上制造的应变Si nMOSFET的自增益也提高了45％，与在4μmSiGe SRB上的应变Si nMOSFET相比，其导通性能提高了25％。在薄SiGe SRB上的应变Si器件中，提取的热阻降低了50％，与在4μmSiGe SRB上制造的器件相比，温升降低了30％。应变Si器件中正自增益的最大漏极电压与ITRS的电源电压缩放预测之间的比较表明，减小SiGe SRB的厚度对于将来的技术节点将是必要的。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
代理获取

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号